The present invention relates to semiconductor electronic devices, and more particularly to clock generating circuits.
Operation of a microprocessor, digital signal processor (DSP) and other integrated circuits, requires a system clock. Many clock generators in high-performance microprocessors employ a phase-locked loop (PLL) in their clock generation schemes to generate a clock signal. Generally, a PLL clock generator has a voltage-controlled oscillator (VCO), and a phase/frequency detector that receives an external reference input signal combined with a feedback input signal from the VCO. The PLL clock generator further includes a charge pump and a loop filter circuit connected in series between the phase/frequency detector and VCO. To generate the clock signal, a first divider circuit receives the VCO output and supplies the feedback input to the phase-frequency detector. A second divider circuit also receives the VCO output and generates the clock signal.
Another known clock generation scheme uses a delay locked loop (DLL). Generally, such systems have an external clock signal fed to a phase detector, a voltage controlled delay line (VCDL), and an input of an exclusive OR (XOR) gate that generates the frequency multiplied clock signal. In this clocking scheme, the phase detector outputs a signal to a loop filter which provides an output signal to the VCDL. The VCDL generates a first output that is fed to the XOR gate to generate a doubled frequency output.
PLL clock generators are known to have several disadvantages in comparison to DLL clock generators. First, a PLL clock generator is a higher-order circuit than a similar DLL clock generator circuit, and as such, is more difficult to design. Second, in a PLL clock generator the loop bandwidth critical for stable operation can change due to process, voltage and temperature variations. Moreover, the VCO output timing uncertainty or jitter accumulates over multiple oscillation cycles and is limited by the time response of the PLL clock generator. Furthermore, as new chip designs operate under increasingly noisy conditions and have delay variations due to power supply/substrate noises, existing PLL clock generators will not be able to provide instantaneous corrections to the delay variations.
DLL clock generators have several inherent advantages over PLL clock generators. DLL clock generators are first-order circuits which are more stable (i.e., have a stable loop operation), and are easily integrated with the loop filter. These advantages enable easier designs of DLL clock generators. Additionally, unlike PLL clock generators, DLL clock generators have no jitter accumulation. Moreover, DLL clock generators are fast locking. While DLL clock generators have advantages as compared to PLL clock generators, PLL generators are preferred for use in generating clock signals due to the difficulty of achieving frequency multiplication using a voltage-control delay line in DLL clock generators.
A delay locked loop (DLL) clock generator circuit is provided for multiplying a frequency of a reference signal inputted into the DLL circuit. The DLL circuit includes a phase detector that receives the reference signal and a feedback signal of the DLL circuit to compare a phase difference or delay between the reference and feedback signals. Based on the phase difference, the phase detector provides a control voltage which is processed by the DLL circuit to generate a control signal. Preferably, the phase detector is reset by presetting gate voltages of the phased detector prior to receiving the feedback and reference signals. Resetting enables the phase detector to have an expanded locking range between the feedback and reference signals. The control signal is delayed at various time intervals to generate a number of delayed signals inputted into a frequency multiplier of the DLL circuit. Using the delayed signals, the frequency multiplier generates an output clock signal that has a frequency that is a multiple of the frequency of the reference signal.